3.7.4@eXgeՉ݌v

           CœK

`̂p

Љ̗p

i2j XL݌v

XL݌viScan Designj

XLpXiScan Pathj

@

eXgeՉ݌viDesign-For-Testabilityj

LSSDiLevel Sensitive Scan Designj

@

SXL݌viFull Scan Designj

RASiRandom Access Scanj

@

XL݌viPartial Scan Designj

IEEE1149.1

@

dXL݌viMultiple Scan Design, Parallel Scan Designj

@

@

EXLiboundary scanj

@

i3j XL݌v

XL݌v

@

KweXg

i4j eXgf[^̈kEWJ

eXgf[^̈kiTest Compressionj

CmCXLiIllinois Scanj

@

@

BASTiBIST Aided Scan Testj

@

@

EDTiEmbedded Deterministic Testj

i5j gݎȃeXg

gݎȃeXgiBuilt-In Self-Test, BISTj

tF[YVt^iPhase Shifterj

@

eXgp^[iPattern Generatorj

@

@

͊iResponse Analyzerj

@

@

_BIST

@

@

`tB[hobNVtgWX^iLFSR, Linear Feedback Shift Registerj

@

@

MISRiMultiple Input Signature Registerj

@

@

V[fBOiReseedingj

@

@

VOl`iSignaturej

@

@

VOl`iSignature Analysisj

@

@

\tgEFABISTiSoftware-Based Self-Test, Instruction-Based Self-Testj

@

i6j eXgeՉ

eXgeՉiSynthesis For Testabilityj

i7j ʃeXgeՉ݌v

ʃeXgeՉ݌viHigh-Level Design-For-Testabilityj

@

샌xeXgeՉ݌viBehavioral Modification For Testabilityj